Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. A solder ball may then be placed on the UBM.
Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, post-passivation interconnect (PPI) lines such as redistribution lines (RDLs) are formed on passivation layers, followed by the formation of polymer films and bumps. Typically, the WLCSP may be bonded onto a printed circuit board (PCB). To be able to have the option of replacing a defective WLCSP bonded on the PCB with a good WLCSP, no underfill material is filled between the WLCSP and the PCB. Such a configuration, however, limits the die size of the current WLCSP technology, because of the thermal mismatch between the die and the PCB, which can induce solder joint cracking during thermal cycling or a drop test. Currently, there is another concern about the stress induced by the passivation structure over the PPI lines, which might impact the device performance and reliability.